1. Field of the Invention
The present invention relates to an imaging apparatus that includes an image sensor.
2. Description of the Related Art
Recently, a complementary metal-oxide semiconductor (CMOS) image sensor has been often used for a digital camera or a video camera. However, various noises are generated in the CMOS image sensor. For example, a dark current noise, a fixed pattern noise due to a reading circuit, or a pixel defect due to a very small flaw unique to the image sensor causes image quality deterioration.
As a countermeasure, there has been offered a method for setting a light-shielded invalid pixel area in the image sensor, and carrying out an arithmetic operation for a pixel signal of a valid pixel area by using a signal obtained by averaging pixel signals of the invalid pixel area. FIG. 11 illustrates an example of a configuration of a pixel area of the CMOS image sensor. The CMOS image sensor includes an invalid pixel area that includes a horizontal optical black (HOP) pixel area 1101 and a vertical optical black (VOB) pixel area 1102, and a valid pixel area 1103.
FIG. 12 is a block diagram illustrating a layout configuration example of the CMOS image sensor. To simplify the description, only nine pixels of 3×3 are shown. In reality, the configuration includes several millions of pixels or more. A vertical shift register 1301 outputs a signal of a row selection line Pres1, Ptx, and Psell to a pixel area 1300. Pixel signals generated at pixels of an odd column of the pixel area 1300 are output to vertical signal lines 1308a and 1308c. Pixel signals generated at pixels of an even column are output to a vertical signal line 1308b. Current sources 1307a to 1307c are connected as loads to the respective vertical signal lines 1308a to 1308c. 
Charge signals output to the vertical signal lines 1308a to 1308c are input to reading circuits 1302 and 1310 respectively corresponding to a channel 1 (CH 1) and a channel 2 (CH 2). Pixel signals of the respective channels are output to differential amplifiers 1305 and 1311 via n channel metal-oxide semiconductor (MOS) transistors 1303a to 1303c. Noise signals of the respective channels are output to the differential amplifiers 1305 and 1311 via n channel metal-oxide semiconductor (MOS) transistors 1304a to 1304c. 
Horizontal shift registers 1306 and 1309 control turning on/off of the transistors 1303a to 1303c and 1304a to 1304c. The differential amplifiers 1305 and 1311 output differences between pixel signals and noise signals. The acquisition of such a difference between the pixel signal and the noise signal enables to acquire an output signal where a noise unique to the CMOS image sensor has been removed.
When there is a variation in characteristics between the current sources connected as the loads to the vertical signal lines or the reading circuits of the respective channels, a level difference almost uniform for each column is generated to appear as a streak-shaped pattern noise extending in a vertical direction (in a column direction). The streak-shaped pattern noise extending in the vertical direction (in the column direction) is a noise unique to the column due to a characteristic variation of paths of a vertical output line and after, and hence it can be corrected by using a signal of the VOB pixel illustrated in FIG. 11. Specifically, Japanese Patent Application Laid-Open No. 2002-016841 discusses a method for canceling a fixed pattern noise by using correction data generated based on output signals from the VOB pixels of a plurality of rows. When the streak-shaped pattern noise extending in the vertical direction (in the column direction) is corrected by the correction method described above, to improve reliability of a correction signal by reducing the influence of a random noise or a flaw pixel signal, a certain number of rows of VOB pixels must be provided.
To achieve low pixelation for image data, pixel addition processing is carried out in the vertical direction (in the column direction) in the image sensor. For the pixel addition processing, Japanese Patent Application Laid-Open No. 2005-86657 discusses a method in which addition is performed at a capacity unit of a column reading circuit, and Japanese Patent Application Laid-Open No. 2010-34895 discusses a method in which addition is performed in a floating diffusion (FD) region connected to a photoelectric conversion unit.
When the pixel addition processing is carried out in the vertical direction (in the column direction), pixel addition processing must be executed in the invalid pixel area including the VOB pixel as in the case of the valid pixel area. Particularly, when the pixel addition is executed in the FD region, because of a difference in FD capacity between the time of addition driving and the time of non-addition driving, a signal level of a dark current included in the charge signal varies between the time of addition driving and the time of non-addition driving. As a result, unless the pixel addition processing is executed in the invalid pixel area as in the case of the valid pixel area to generate a correction signal, correct correction processing cannot be carried out.
Further, to calculate highly reliable correction data even when the pixel addition processing is executed, more pixels must be provided, creating a problem of an increase of a chip area.